LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 770

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.4.3.5 Vector Table Offset Register
Table 657. ICSR bit assignments
[1]
When you write to the ICSR, the effect is unpredictable if you:
The VTOR indicates the offset of the vector table base address from memory address
0x00000000. See the register summary in
The bit assignments are shown in
Bits
[25]
[24]
[23]
[22]
[21:18] -
[17:12] VECTPENDING
[11]
[10:9]
[8:0]
•
•
This is the same value as IPSR bits[8:0], see
write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
Name
PENDSTCLR
-
Reserved for
Debug use
ISRPENDING
RETTOBASE
-
VECTACTIVE
All information provided in this document is subject to legal disclaimers.
[1]
Rev. 2 — 19 August 2010
Type
WO
-
RO
RO
-
RO
RO
-
RO
Function
SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
Reserved.
This bit is reserved for Debug use and reads-as-zero when
the processor is not in Debug.
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
Reserved.
Indicates the exception number of the highest priority pending
enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
The value indicated by this field includes the effect of the
BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
Indicates whether there are preempted active exceptions:
0 = there are preempted active exceptions to execute
1 = there are no active exceptions, or the currently-executing
exception is the only active exception.
Reserved.
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
exception.
Remark: Subtract 16 from this value to obtain the IRQ
number required to index into the Interrupt Clear-Enable,
Set-Enable, Clear-Pending, Set-Pending, or Priority
Registers, see
Table
658.
Table 629 “IPSR bit
Table 654
Chapter 34: Appendix: Cortex-M3 user guide
Table 629 “IPSR bit
for its attributes.
assignments”.
[1]
assignments”.
of the currently active
UM10360
© NXP B.V. 2010. All rights reserved.
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