LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 495

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 428. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,
UM10360
User manual
Bit
3:2
31:4
Symbol
Count
Input
Select
-
0x4009 4070) bit description
21.6.4 Timer Counter registers (T0TC - T3TC, 0x4000 4008, 0x4000 8008,
21.6.5 Prescale register (T0PR - T3PR, 0x4000 400C, 0x4000 800C,
21.6.6 Prescale Counter register (T0PC - T3PC, 0x4000 4010, 0x4000 8010,
Value Description
00
01
10
11
-
0x4009 0008, 0x4009 4008)
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect an
overflow if needed.
0x4009 000C, 0x4009 400C)
The 32-bit Prescale register specifies the maximum value for the Prescale Counter.
0x4009 0010, 0x4009 4010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship of the resolution of the
timer versus the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 pclks
when PR = 1, etc.
When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for
clocking.
CAPn.0 for TIMERn
CAPn.1 for TIMERn
Reserved
Reserved
Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits
for that input in the Capture Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
same timer.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 21: LPC17xx Timer 0/1/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
00
NA