LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 28

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
3.7 Other system controls and status flags
UM10360
User manual
3.7.1 System Controls and Status register (SCS - 0x400F C1A0)
Some aspects of controlling LPC17xx operation that do not fit into peripheral or other
registers are grouped here.
The SCS register contains several control/status bits related to the main oscillator. Since
chip operation always begins using the Internal RC Oscillator, and the main oscillator may
not be used at all in some applications, it will only be started by software request. This is
accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13.
The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that
software can determine when the oscillator is running and stable. At that point, software
can control switching to the main oscillator as a clock source. Prior to starting the main
oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
Table 13.
Bit
3:0
4
5
6
31:7 -
Symbol
-
OSCRANGE
OSCEN
OSCSTAT
System Controls and Status register (SCS - address 0x400F C1A0) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
-
0
1
0
1
0
1
-
Rev. 2 — 19 August 2010
Reserved. User software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
Main oscillator range select.
The frequency range of the main oscillator is 1 MHz
to 20 MHz.
The frequency range of the main oscillator is
15 MHz to 25 MHz.
Main oscillator enable.
The main oscillator is disabled.
The main oscillator is enabled, and will start up if
the correct external circuitry is connected to the
XTAL1 and XTAL2 pins.
Main oscillator status.
The main oscillator is not ready to be used as a
clock source.
The main oscillator is ready to be used as a clock
source. The main oscillator must be enabled via the
OSCEN bit.
Reserved. User software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
Chapter 3: LPC17xx System control
UM10360
© NXP B.V. 2010. All rights reserved.
Access Reset
-
R/W
R/W
RO
-
28 of 840
value
NA
0
0
0
NA