LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 443

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
19.8.3 I
19.8.4 I
Table 385. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the
I2CONSET register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
I2C1STAT - 0x4005 C004; I
Each I
Status register is read-only.
Table 386. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
0x4005 C008; I
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Bit
4
5
6
31:7
Bit
2:0
7:3
31:8
2
2
C Status register (I2STAT: I
C Data register (I2DAT: I
2
Symbol Description
-
STAC
I2ENC
-
Symbol Description
-
Status
-
C Status register reflects the condition of the corresponding I
I2C1CONCLR - 0x4005 C018; I
0x4005 C004; I
2
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
C Control Clear register (I2CONCLR: I
C Status register (I2STAT: I
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
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Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
These bits are unused and are always 0.
These bits give the actual status information about the I
Reserved. The value read from a reserved bit is not defined.
2
C interface Disable bit.
2
C2, I2C2DAT - 0x400A 0008)
Rev. 2 — 19 August 2010
2
C2, I2C2STAT - 0x400A 0004) bit description
2
C states. When any of these states entered, the SI bit will
2
C0, I2C0DAT - 0x4001 C008; I
2
C2, I2C2STAT - 0x400A 0004)
2
C0, I2C0STAT - 0x4001 C004; I
2
C0, I2C0STAT - 0x4001 C004; I
2
C2, I2C2CONCLR - 0x400A 0018) bit description
2
C0, I2C0CONCLR - 0x4001 C018; I
Chapter 19: LPC17xx I2C0/1/2
Table 398
2
C interface.
2
2
C1, I2C1STAT -
C interface. The I
UM10360
2
© NXP B.V. 2010. All rights reserved.
C1, I2C1DAT -
to
Table
2
C1,
443 of 840
401.
2
NA
Reset
value
0
0x1F
C1,
2
C