LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 488

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
20.8 FIFO controller
UM10360
User manual
Fig 112. 4-wire receiver slave mode sharing the transmitter bit clock and WS
Handling of data for transmission and reception is performed via the FIFO controller which
can generate two DMA requests and an interrupt request. The controller consists of a set
of comparators which compare FIFO levels with depth settings contained in registers. The
current status of the level comparators can be seen in the APB status register.
Table 421. Conditions for FIFO level comparison
System signaling occurs when a level detection is true and enabled.
Table 422. DMA and interrupt request generation
Table 423. Status feedback in the I2SSTATE register
Level Comparison
dmareq_tx_1
dmareq_rx_1
dmareq_tx_2
dmareq_rx_2
irq_tx
irq_rx
System Signaling
irq
dmareq[0]
dmareq[1]
Status Feedback
irq
dmareq1
dmareq2
TX bit clock
All information provided in this document is subject to legal disclaimers.
peripheral
Rev. 2 — 19 August 2010
(receive)
block
I
2
S
Condition
tx_depth_dma1 >= tx_level
rx_depth_dma1 <= rx_level
tx_depth_dma2 >= tx_level
rx_depth_dma2 <= rx_level
tx_depth_irq >= tx_level
rx_depth_irq <= rx_level
Condition
(irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable)
(dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &
rx_dma1_enable )
( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &
rx_dma2_enable )
Status
irq_rx | irq_tx
(dmareq_tx_1 | dmareq_rx_1)
(dmareq_rx_2 | dmareq_tx_2)
TX_WS ref
I2SRX_SDA
I2SRX_WS
Chapter 20: LPC17xx I2S
UM10360
© NXP B.V. 2010. All rights reserved.
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