LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 404

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
17.6 SPI peripheral details
UM10360
User manual
17.6.1 General information
17.6.2 Master operation
There are five control and status registers for the SPI port. They are described in detail in
Section 17.7 “Register description” on page
The SPI Control Register (S0SPCR) contains a number of programmable bits used to
control the function of the SPI block. The settings for this register must be set up prior to a
given data transfer taking place.
The SPI Status Register (S0SPSR) contains read-only bits that are used to monitor the
status of the SPI interface, including normal functions, and exception conditions. The
primary purpose of this register is to detect completion of a data transfer. This is indicated
by the SPI Interrupt Flag (SPIF) in the S0SPINT register. The remaining bits in the register
are exception condition indicators. These exceptions will be described later in this section.
The SPI Data Register (S0SPDR) is used to provide the transmit and receive data bytes.
An internal shift register in the SPI block logic is used for the actual transmission and
reception of the serial data. Data is written to the SPI Data Register for the transmit case.
There is no buffer between the data register and the internal shift register. A write to the
data register goes directly into the internal shift register. Therefore, data should only be
written to this register when a transmit is not currently in progress. Read data is buffered.
When a transfer is complete, the receive data is transferred to a single byte data buffer,
where it is later read. A read of the SPI Data Register returns the value of the read data
buffer.
The SPI Clock Counter Register (S0SPCCR) controls the clock rate when the SPI block is
in master mode. This needs to be set prior to a transfer taking place, when the SPI block
is a master. This register has no function when the SPI block is a slave.
Prior to use, SPI configurations such as the master/slave settings, clock polarity, clock
rate, etc. must be set up in the SPI Control Register and SPI Clock Counter Register.
The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI
option is not implemented in this design. When a device is set up to be a slave, its I/Os are
only active when it is selected by the SSEL signal being active.
The following sequence can be followed to set up the SPI prior to its first use as a master.
This is typically done during program initialization.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be the master. This process assumes that any prior data transfer
has already completed.
1. Set the SPI Clock Counter Register to the desired clock rate.
2. Set the SPI Control Register to the desired settings for master mode.
1. Optionally, verify the SPI setup before starting the transfer.
2. Write the data to transmitted to the SPI Data Register. This write starts the SPI data
transfer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
406.
Chapter 17: LPC17xx SPI
UM10360
© NXP B.V. 2010. All rights reserved.
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