LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 573

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 528: Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description
28.5 Block diagram
UM10360
User manual
Bit
1:0
30:2
31
Symbol
WDSEL
-
WDLOCK
Value Description
00
01
10
11
-
0
1
The block diagram of the Watchdog is shown below in the
synchronization logic (PCLK - WDCLK) is not shown in the block diagram.
Fig 132. Watchdog block diagram
internal RC oscillator
These bits select the clock source for the Watchdog timer as described below.
Warning: Improper setting of this value may result in incorrect operation of the
Watchdog timer, which could adversely affect system operation. If the WDLOCK bit in
this register is set, the WDSEL bit cannot be modified.
Selects the Internal RC oscillator (irc_clk) as the Watchdog clock source (default).
Selects the APB peripheral clock (watchdog pclk) as the Watchdog clock source.
Selects the RTC oscillator (rtc_clk) as the Watchdog clock source.
Reserved, this setting should not be used.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
This bit is set to 0 on any reset. It cannot be cleared by software.
Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register
cannot be modified.
RTC oscillator
pclk
All information provided in this document is subject to legal disclaimers.
WDCLKSEL
feed sequence
Rev. 2 — 19 August 2010
WDFEED
feed error
feed ok
wdclk
Chapter 28: LPC17xx Watchdog Timer (WDT)
÷ 4
WDINT WDTOF WDRESET
32-BIT DOWN COUNTER
Figure
underflow
WMOD register
WDTC
WDTV
132. The
SHADOW BIT
UM10360
© NXP B.V. 2010. All rights reserved.
WDEN
enable
count
573 of 840
reset
interrupt
Reset
Value
0
NA
0