LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 515

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 445. PWM1 register map
Table 446: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description
UM10360
User manual
Generic
Name
MR4
MR5
MR6
PCR
LER
CTCR
Bit
0
1
2
3
4
5
7:6
8
9
10
31:11 -
Symbol
PWMMR0 Interrupt Interrupt flag for PWM match channel 0.
PWMMR1 Interrupt Interrupt flag for PWM match channel 1.
PWMMR2 Interrupt Interrupt flag for PWM match channel 2.
PWMMR3 Interrupt Interrupt flag for PWM match channel 3.
PWMCAP0
Interrupt
PWMCAP1
Interrupt
-
PWMMR4 Interrupt Interrupt flag for PWM match channel 4.
PWMMR5 Interrupt Interrupt flag for PWM match channel 5.
PWMMR6 Interrupt Interrupt flag for PWM match channel 6.
Description
Match Register 4. MR4 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM4 in either
edge mode, and sets PWM5 if it’s in double-edge mode.
Match Register 5. MR5 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM5 in either
edge mode, and sets PWM6 if it’s in double-edge mode.
Match Register 6. MR6 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM6 in either
edge mode.
PWM Control Register. Enables PWM outputs and selects PWM channel
types as either single edge or double edge controlled.
Load Enable Register. Enables use of new PWM match values.
Count Control Register. The CTCR selects between Timer and Counter
mode, and in Counter mode selects the signal and edge(s) for counting.
24.6.1 PWM Interrupt Register (PWM1IR - 0x4001 8000)
[1]
The PWM Interrupt Register consists of 11 bits
4 reserved for the future use. If an interrupt is generated then the corresponding bit in the
PWMIR will be high. Otherwise, the bit will be low. Writing a logic 1 to the corresponding
IR bit will reset the interrupt. Writing a 0 has no effect.
Description
Interrupt flag for capture input 0
Interrupt flag for capture input 1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
(Table
446), 7 for the match interrupts and
R/W
Access Reset
R/W
R/W
R/W
R/W
R/W
0
Value
0
0
0
0
0
[1]
UM10360
© NXP B.V. 2010. All rights reserved.
PWMn Register
Name & Address
PWM1MR4 -
0x4001 8040
PWM1MR5 -
0x4001 8044
PWM1MR6 -
0x4001 8048
PWM1PCR -
0x4001 804C
PWM1LER -
0x4001 8050
PWM1CTCR -
0x4001 8070
515 of 840
Reset
Value
0
0
0
0
0
0
NA
0
0
0
NA