MC68HC908QY1VDTE Freescale Semiconductor, MC68HC908QY1VDTE Datasheet - Page 27

IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part Number
MC68HC908QY1VDTE
Description
IC MCU 1.5K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY1VDTE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
16-TSSOP
Processor Series
HC08Q
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
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2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in
Additional I/O registers have these addresses:
Freescale Semiconductor
$0000
$0001
$0002
$0003
$0004
$0005
Addr.
$FE00 — Break status register, BSR
$FE01 — Reset status register, SRSR
$FE02 — Break auxiliary register, BRKAR
$FE03 — Break flag control register, BFCR
$FE04 — Interrupt status register 1, INT1
$FE05 — Interrupt status register 2, INT2
$FE06 — Interrupt status register 3, INT3
$FE07 — Reserved
$FE08 — FLASH control register, FLCR
$FE09 — Break address register high, BRKH
$FE0A — Break address register low, BRKL
$FE0B — Break status and control register, BRKSCR
$FE0C — LVI status register, LVISR
$FE0D — Reserved
$FFBE — FLASH block protect register, FLBPR
$FFC0 — Internal OSC trim value (factory programmed, VDD = 5.0 V)
$FFC1 — Internal OSC trim value (factory programmed, VDD = 3.0 V)
$FFFF — COP control register, COPCTL
Data Direction Register A
Data Direction Register B
Register Name
Port A Data Register
Port B Data Register
Unimplemented
Unimplemented
See page 100.
See page 101.
See page 98.
See page 98.
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
(DDRA)
(DDRB)
(PTA)
(PTB)
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
MC68HC908QY/QT Family Data Sheet, Rev. 6
DDRB7
PTB7
Bit 7
Figure
R
R
0
0
= Unimplemented
2-2, contain most of the control, status, and data registers.
DDRB6
AWUL
PTB6
R
6
0
0
DDRA5
DDRB5
PTA5
PTB5
0
5
0
DDRA4
DDRB4
Unaffected by reset
Unaffected by reset
PTA4
PTB4
R
4
0
0
= Reserved
DDRA3
DDRB3
PTA3
PTB3
3
0
0
DDRB2
PTA2
PTB2
U = Unaffected
Input/Output (I/O) Section
2
0
0
0
DDRA1
DDRB1
PTA1
PTB1
1
0
0
DDRA0
DDRB0
PTA0
PTB0
Bit 0
0
0
27

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