IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part NumberMC68HC908QY1VDTE
DescriptionIC MCU 1.5K FLASH 16-TSSOP
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QY1VDTE datasheet
 

Specifications of MC68HC908QY1VDTE

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o13Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 105°CPackage / Case16-TSSOP
Processor SeriesHC08QCoreHC08
Data Bus Width8 bitData Ram Size128 B
Maximum Clock Frequency8 MHzNumber Of Programmable I/os14
Number Of Timers2Maximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
Connectivity-  
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Page 86/184

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Low-Voltage Inhibit (LVI)
V
. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
TRIPF
Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, V
for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, V
operation. The actual trip thresholds are specified in
DC Electrical
Characteristics.
After a power-on reset, the LVI’s default mode of operation is 3 volts. If a
5-V system is used, the user must set the LVI5OR3 bit to raise the trip point
to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset
while the V
supply is not above the V
DD
microcontroller unit (MCU) will immediately go into reset. The next time the
LVI releases the reset, the supply will be above the V
Once an LVI reset occurs, the MCU remains in reset until V
causes the MCU to exit reset. See
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,
and the LVIRSTD bit must be at set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V
DD
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
rises above the rising trip point voltage, V
DD
continually entering and exiting reset if V
V
by the hysteresis voltage, V
TRIPF
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V
See
16.5 5-V DC Electrical Characteristics
Characteristics
for the actual trip point voltages.
86
16.5 5-V DC Electrical Characteristics
NOTE
for 5-V mode, the
TRIPR
DD
Chapter 13 System Integration Module (SIM)
levels below the V
DD
TRIPF
to remain above the V
level, enabling LVI resets allows the LVI
TRIPF
falls below the V
level. In the configuration register, the
DD
TRIPF
fall below V
), the LVI will maintain a reset condition until
DD
TRIPF
. This prevents a condition in which the MCU is
TRIPR
is approximately equal to V
DD
.
HYS
NOTE
[5 V] or V
[3 V]) may be lower than this.
TRIPF
TRIPF
and
MC68HC908QY/QT Family Data Sheet, Rev. 6
, to be configured
TRIPF
, to be configured for 3-V
TRIPF
and
for 5-V mode.
TRIPR
rises above a voltage, V
, which
TRIPR
for the reset recovery
level, software can monitor V
DD
. V
is greater than
TRIPF
TRIPR
16.9 3-V DC Electrical
Freescale Semiconductor
16.9 3-V
by polling