MC68HC908QY1VDTE Freescale Semiconductor, MC68HC908QY1VDTE Datasheet - Page 86

IC MCU 1.5K FLASH 16-TSSOP

MC68HC908QY1VDTE

Manufacturer Part Number
MC68HC908QY1VDTE
Description
IC MCU 1.5K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY1VDTE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
16-TSSOP
Processor Series
HC08Q
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
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V
Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, V
for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, V
operation. The actual trip thresholds are specified in
DC Electrical
Once an LVI reset occurs, the MCU remains in reset until V
causes the MCU to exit reset. See
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,
and the LVIRSTD bit must be at set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
continually entering and exiting reset if V
V
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
86
Low-Voltage Inhibit (LVI)
TRIPF
DD
TRIPF
rises above the rising trip point voltage, V
. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
by the hysteresis voltage, V
Characteristics.
After a power-on reset, the LVI’s default mode of operation is 3 volts. If a
5-V system is used, the user must set the LVI5OR3 bit to raise the trip point
to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset
while the V
microcontroller unit (MCU) will immediately go into reset. The next time the
LVI releases the reset, the supply will be above the V
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V
See
Characteristics
16.5 5-V DC Electrical Characteristics
DD
DD
supply is not above the V
for the actual trip point voltages.
TRIPF
to remain above the V
MC68HC908QY/QT Family Data Sheet, Rev. 6
DD
HYS
Chapter 13 System Integration Module (SIM)
DD
falls below the V
[5 V] or V
levels below the V
.
DD
DD
fall below V
is approximately equal to V
TRIPR
TRIPF
NOTE
NOTE
. This prevents a condition in which the MCU is
[3 V]) may be lower than this.
16.5 5-V DC Electrical Characteristics
TRIPF
TRIPF
TRIPR
TRIPF
TRIPF
and
level. In the configuration register, the
DD
), the LVI will maintain a reset condition until
level, enabling LVI resets allows the LVI
for 5-V mode, the
level, software can monitor V
16.9 3-V DC Electrical
rises above a voltage, V
TRIPR
TRIPF
TRIPF
for 5-V mode.
. V
TRIPR
, to be configured for 3-V
for the reset recovery
TRIPF
Freescale Semiconductor
is greater than
, to be configured
TRIPR
and
DD
, which
by polling
16.9 3-V

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