MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 111

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

9.3.2 Data Direction Register B
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
TCH0 — Timer Channel I/O Bit
TCLK — Timer Clock Bit
MCLK — Bus Clock Bit
Data direction register B (DDRB) determines whether each port B pin is an input or
an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding
port B pin; a 0 disables the output buffer.
MCLKEN — MCLK Enable Bit
DDRB[3:0] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before changing
data direction register B bits from 0 to 1.
Figure 9-7
The PTB2/TCH0 pin is the TIM channel 0 input capture/output compare pin. The
edge/level select bits, ELS0B:ELS0A, determine whether the PTB2/TCH0 pin is
a timer channel I/O or a general-purpose I/O pin. See
Interface Module
The PTB3/TCLK pin is the external clock input for TIM. The prescaler select bits,
PS[2:0], select PTB3/TCLK as the TIM clock input. (See
Control
available for general-purpose I/O.
The bus clock (MCLK) is driven out of pin PTB0/MCLK when enabled by the
MCLKEN bit in port B data direction register bit 7.
This read/write bit enables MCLK to be an output signal on PTB0. If MCLK is
enabled, PTB0 is under the control of MCLKEN. Reset clears this bit.
These read/write bits control port B data direction. Reset clears DDRB[3:0],
configuring all port B pins as inputs.
Address:
Reset:
Read:
Write:
1 = MCLK output enabled
0 = MCLK output disabled
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Freescale Semiconductor, Inc.
For More Information On This Product,
MCLKEN
shows the port B I/O logic.
Register.) When not selected as the TIM clock, PTB3/TCLK is
$0005
Bit 7
0
Figure 9-6. Data Direction Register B (DDRB)
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= Unimplemented
Input/Output (I/O) Ports
(TIM).
6
0
0
5
0
4
0
DDRB3
3
0
DDRB2
Section 11. Timer
2
0
11.8.1 TIM Status and
Input/Output (I/O) Ports
DDRB1
1
0
Data Sheet
DDRB0
Bit 0
Port B
0
111