MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 96

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Keyboard/External Interrupt Module (KBI)
7.3.2 IRQ Pin
Data Sheet
96
NOTE:
The IRQ1 pin and keyboard interrupt pins are falling-edge triggered and are
software-configurable to be both falling-edge and low-level triggered. The MODEI
and MODEK bits in the INTKBSCR controls the triggering sensitivity of the IRQ pin
and keyboard interrupt pins.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a
vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt
latch remains set until both of these occur:
The vector fetch or software clear may occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending. A reset
will clear the latch, the MODEI and MODEK control bits, thereby clearing the
interrupt even if the pin stays low.
When set, the IMASKI and IMASKK bits in the INTKBSCR mask all external
interrupt requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK<x> bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests. See
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ1 latch. A vector
fetch, software clear, or reset clears the IRQ1 latch. If the MODEI bit is set, the IRQ
pin is both falling-edge sensitive and low-level sensitive. With MODEI set, both of
these actions must occur to clear the IRQ1 latch:
The vector fetch or software clear and the return of the IRQ pin to logic 1 can occur
in any order. The interrupt request remains pending as long as the IRQ pin is at
logic 0. A reset will clear the latch and the MODEI control bit, thereby clearing the
interrupt even if the pin stays low.
•
•
•
•
Vector fetch or software clear
Return of the interrupt pin to logic 1
Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software may generate the interrupt
acknowledge signal by writing a 1 to the ACKI bit in the IRQ and keyboard
status and control register (INTKBSCR). The ACKI bit is useful in
applications that poll the IRQ pin and require software to clear the IRQ1
latch. Writing to the ACKI bit can also prevent spurious interrupts due to
noise. Setting ACKI does not affect subsequent transitions on the IRQ pin.
A falling edge on IRQ that occurs after writing to the ACKI bit latches another
interrupt request. If the IRQ1 mask bit, IMASKI, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the
IRQ1 latch remains set.
Freescale Semiconductor, Inc.
For More Information On This Product,
Keyboard/External Interrupt Module (KBI)
Go to: www.freescale.com
Figure
MC68HC908RF2 — Rev. 4.0
7-4.
MOTOROLA