MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 137

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

11.5 Interrupts
11.5.1 Low-Power Modes
11.5.2 Wait Mode
MC68HC908RF2 — Rev. 4.0
MOTOROLA
signal generation when changing the PWM pulse width to a new, much larger
value.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM
operation. The TIM channel 0 registers (TCH0H and TCH0L) initially control the
buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors
the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows.
Subsequent output compares try to force the output to a state it is already in and
have no effect. The result is a 0 percent duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit
generates a 100 percent duty cycle output. See
Control
These TIM sources can generate interrupt requests:
The WAIT and STOP instructions put the MCU in low power- consumption standby
modes.
The TIM remains active after the execution of a WAIT instruction. In wait mode, the
TIM registers are not accessible by the CPU. Any enabled CPU interrupt request
from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by
stopping the TIM before executing the WAIT instruction.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
•
•
TIM overflow flag (TOF) — The timer overflow flag (TOF) bit is set when the
TIM counter reaches the modulo value programmed in the TIM counter
modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM
overflow interrupt requests. TOF and TOIE are in the TIM status and control
registers.
TIM channel flag (CH0F) — The CH0F bit is set when an input capture or
output compare occurs on channel. Channel TIM CPU interrupt requests
are controlled by the channel interrupt enable bit, CH1IE.
Freescale Semiconductor, Inc.
Registers.
For More Information On This Product,
Go to: www.freescale.com
Timer Interface Module (TIM)
11.8.4 TIM Channel Status and
Timer Interface Module (TIM)
Data Sheet
Interrupts
137