MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 78

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Internal Clock Generator Module (ICG)
6.4.3 Clock Monitor Interrupts
6.4.4 Quantization Error in DCO Output
6.4.4.1 Digitally Controlled Oscillator
Data Sheet
78
The clock monitor circuit can be used to recover from perilous situations such as
crystal loss. To use the clock monitor effectively, these notes should be observed:
The digitally controlled oscillator (DCO) is comprised of three major sub-blocks:
Each of these blocks affects the clock period of the internal clock (ICLK). Since
these blocks are controlled by the digital loop filter (DLF) outputs DDIV and DSTG,
the output of the DCO can change only in quantized steps as the DLF increments
or decrements its output. The following sections describe how each block will affect
the output frequency.
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates
the internal clock (ICLK), whose clock period is dependent on the digital loop filter
outputs (DSTG[7:0] and DDIV[3:0]). Because of the digital nature of the DCO, the
clock period of ICLK will change in quantized steps. This will create a clock period
difference or quantization error (Q-ERR) from one cycle to the next. Over several
cycles or for longer periods, this error is divided out until it reaches a minimum error
of 0.202 percent to 0.368 percent. The dependence of this error on the DDIV[3:0]
value and the number of cycles the error is measured over is shown in
1. Binary weighted divider
2. Variable-delay ring oscillator
3. Ring oscillator fine-adjust circuit
•
•
•
•
•
Enable the clock monitor and clock monitor interrupts.
The first statement in the clock monitor interrupt service routine should be a
read to the ICG control register (ICGCR) to verify that the clock monitor flag
(CMF) is set. This is also the first step in clearing the CMF bit.
Never use BSET or BCLR instructions on the ICGCR, as this may
inadvertently clear CMF. Only use the BRSET and BRCLR instructions to
check the CMF bit and not to check any other bits in the ICGCR.
When the clock monitor detects inactivity on the selected clock source
(defined by the CS bit of the ICG control register), the inactive clock is
deselected automatically and the remaining active clock is selected as the
source for CGMXCLK. The interrupt service routine can use the state of the
CS bit to check which clock is inactive.
When the clock monitor detects inactivity, the application may have been
subjected to extreme conditions which may have affected other circuits. The
clock monitor interrupt service routine should take any appropriate
precautions.
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Clock Generator Module (ICG)
Go to: www.freescale.com
MC68HC908RF2 — Rev. 4.0
Table
MOTOROLA
6-3.