MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 73

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

MC68HC908RF2 — Rev. 4.0
MOTOROLA
ICGON ECGON ECGS EXTSLOW
U: Unaffected. Refer to section of table where ICGON or ECGON is set to x (don’t care).
IBASE is always used as the internal frequency (307.2 kHz).
0
x
x
x
x
0
x
x
x
x
NOTE:
x
0
0
1
1
the low-frequency base clock (IBASE) is used in place of ICLK because it always
operates at or near 307.2 kHz. For proper operation, EREF must be at least twice
as slow as IBASE and IREF must be at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one
of the signals is divided down. Which signal is divided and by how much is
determined by the external slow (EXTSLOW) bit in the configuration register,
according to the rules in
always divided by four. A longer divider is used on either IBASE or ECLK based on
the EXTSLOW bit.
If EXTSLOW is not set according to the rules defined in
monitor could switch clock sources unexpectedly.
The long divider (divide by 4096) is also used as an external crystal stabilization
divider. The divider is reset when the external clock generator is off (ECGEN is
clear). When the external clock generator is first turned on, the external clock
generator stable bit (ECGS) will be clear. This condition automatically selects
ECLK as the input to the long divider. The external stabilization clock (ESTBCLK)
will be ECLK divided by 4096. This timeout allows the crystal to stabilize. The falling
edge of ESTBCLK is used to set ECGS. (ECGS will set after a full 16 or 4096
cycles.) When ECGS is set, the divider returns to its normal function. ESTBCLK
may be generated by either IBASE or ECLK, but any clocking will reinforce only the
set condition. If ECGS is cleared because the clock monitor determined that ECLK
was inactive, the divider will revert to a stabilization divider. Since this will change
the EREF and IREF divide ratios, it is important to turn the clock monitor off
(CMON = 0) after inactivity is detected to ensure valid recovery.
Table 6-2. Clock Monitor Reference Divider Ratios
x
x
x
0
1
Freescale Semiconductor, Inc.
Max 8 MHz
Max 8 MHz
Max 100 kHz
Min 30 kHz
Min 1 MHz
Min 30 kHz
For More Information On This Product,
Frequency
External
Internal Clock Generator Module (ICG)
U
0
Go to: www.freescale.com
Divider
EREF
128*4
Ratio
1*4
Off
Off
U
Table
Frequency
1.953 kHz
15.63 kHz
25.0 kHz
7.5 kHz
6-2. Note that each signal (IBASE and ECLK) is
EREF
U
0
0
ESTBCLK
(IBASE)
Divider
(ECLK)
(ECLK)
Ratio
4096
4096
4096
Off
U
Internal Clock Generator Module (ICG)
Frequency
ESTBCLK
1.875 kHz
1.953 kHz
500 kHz
244 Hz
75 Hz
±25%
U
0
Table
Divider
Functional Description
Ratio
IREF
16*4
1*4
1*4
Off
6-2, the clock
U
76.8 kHz ±25%
76.8 kHz ±25%
Frequency
4.8 kHz
Data Sheet
±25%
IREF
U
0
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