MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 138

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Timer Interface Module (TIM)
11.5.3 Stop Mode
11.6 TIM During Break Interrupts
11.7 I/O Signals
11.7.1 TIM Clock Pin (TCLK)
Data Sheet
138
The TIM is inactive after the execution of a STOP instruction. The STOP instruction
does not affect register conditions or the state of the TIM counter. TIM operation
resumes when the MCU exits stop mode after an external interrupt.
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR) enables software to clear status bits during the break state. See
10.7.3 SIM Break Flag Control
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE
bit. If a status bit is cleared during the break state, it remains cleared when the MCU
exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), software can read and write I/O registers during the break
state without affecting status bits. Some status bits have a 2-step read/write
clearing procedure. If software does the first step on such a bit before the break,
the bit cannot change during the break state as long as BCFE is at 0. After the
break, doing the second step clears the status bit.
Port B shares two of its pins with the TIM. TCLK can be used as an external clock
input to the TIM prescaler and the TIM channel 0 I/O pin PTB2/TCH0.
TCLK is an external clock input that can be the clock source for the TIM counter
instead of the prescaled internal bus clock. Select the TCLK input by writing 1s to
the three prescaler select bits, PS2–PS0. See
Register. The minimum TCLK pulse width, TCLK
The maximum TCLK frequency is:
Refer to
TCLK is available as a general-purpose I/O pin when not used as the TIM clock
input. When the TCLK pin is the TIM clock input, it is an input regardless of the state
of the DDRB3 bit in data direction register B.
bus frequency ÷ 2
Freescale Semiconductor, Inc.
14.9 Control
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Timer Interface Module (TIM)
Timing.
bus frequency
Register.
1
11.8.1 TIM Status and Control
+ t
LMIN
su
or TCLK
MC68HC908RF2 — Rev. 4.0
HMIN
, is:
MOTOROLA