MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 136

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Timer Interface Module (TIM)
11.4.8 Buffered PWM Signal Generation
11.4.9 PWM Initialization
Data Sheet
136
NOTE:
NOTE:
Channels 0 and 1 can be linked to form a buffered PWM channel whose output
appears on the TCH0 pin. The TIM channel registers of the linked pair alternately
control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links
channel 0 and channel 1. The TIM channel 0 registers initially control the pulse
width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM
channel 1 registers to synchronously control the pulse width at the beginning of the
next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls and monitors
the buffered PWM function, and TIM channel 1 status and control register (TSC1)
is unused.
In buffered PWM signal generation, do not write new pulse width values to the
currently active channel registers. User software should track the currently active
channel to prevent writing a new value to the active channel. Writing to the active
channel registers is the same as generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered PWM signals,
use this initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0 percent duty cycle
generation and removes the ability of the channel to self-correct in the event of
software error or noise. Toggling on output compare can also cause incorrect PWM
1. In the TIM status and control register (TSC):
2. In the TIM counter modulo registers (TMODH and TMODL), write the value
3. In the TIM channel x registers (TCHxH and TCHxL), write the value for the
4. In TIM channel x status and control register (TSCx):
for the required PWM period.
required pulse width.
Freescale Semiconductor, Inc.
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit,
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare)
For More Information On This Product,
TRST.
buffered output compare or PWM signals) to the mode select bits,
MSxB and MSxA. See
to the edge/level select bits, ELSxB and ELSxA. The output action on
compare must force the output to the complement of the pulse width
level. See
Go to: www.freescale.com
Timer Interface Module (TIM)
Table
11-3.
Table
11-3.
MC68HC908RF2 — Rev. 4.0
MOTOROLA