MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 81

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

6.4.6 Nominal Frequency Settling Time
6.4.6.1 Settling to Within 15 Percent
MC68HC908RF2 — Rev. 4.0
MOTOROLA
Because the clock period of the internal clock (ICLK) is dependent on the digital
loop filter outputs (DDIV and DSTG) which cannot change instantaneously, ICLK
will temporarily operate at an incorrect clock period when any of the operating
condition changes. This happens whenever the part is reset, the ICG multiply factor
(N) is changed, the ICG trim factor (TRIM) is changed, or the internal clock is
enabled after inactivity (STOP or disabled operation). The time that the ICLK takes
to adjust to the correct period is known as the settling time.
Settling time depends primarily on how many corrections it takes to change the
clock period, and the period of each correction. Since the corrections require four
periods of the low-frequency base clock (4*t
multiply factor for the desired frequency) times faster than IBASE, each correction
takes 4*N*t
When the error is greater than 15 percent, the filter takes eight corrections to
double or halve the clock period. Due to how the DCO increases or decreases the
clock period, the total period of these eight corrections is approximately 11 times
the period of the fastest correction. (If the corrections were perfectly linear, the total
period would be 11.5 times the minimum period; however, the ring must be slightly
non-linear.) Therefore, the total time it takes to double or halve the clock period is
44*N*t
If the clock period needs more than doubled or halved, the same relationship
applies, only for each time the clock period needs doubled, the total number of
cycles doubles.
That is, when transitioning from fast to slow:
This series can be expressed as (2
times the speed needs doubled or halved. Since 2
t
that increasing speed takes much longer than decreasing speed since N is higher.
This can be expressed in terms of the initial clock period (t
period (t
ICLKSLOW
•
•
•
ICLKFAST
Going from the initial speed to half speed takes 44*N*t
From half speed to quarter speed takes 88*N*t
Going from quarter speed to eighth speed takes 176*N*t
on.
Freescale Semiconductor, Inc.
2
For More Information On This Product,
) as such:
/t
ICLK
ICLKFAST
Internal Clock Generator Module (ICG)
.
. The period of ICLK, however, will vary as the corrections occur.
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, the equation reduces to 44*N*(t
t
15
=
x
abs 44N t
–1)*44*N*t
[
IBASE
(
1
Internal Clock Generator Module (ICG)
ICLKFAST
–
), and since ICLK is N (the ICG
t
x
2
)
happens to be equal to
]
ICLKSLOW
ICLKFAST
, where x is the number of
1
) minus the final clock
ICLKFAST
-t
ICLKFAST
ICLKFAST
Usage Notes
, and so
). Note
Data Sheet
81