MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet - Page 145

• Manufacturer Part Number: MC68HC908RF2MFA
• Description: IC MCU 2K FLASH 4MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908RF2MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: LVD, POR, PWM, RF Mod
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

11.8.5 TIM Channel Registers
MC68HC908RF2 — Rev. 4.0
MOTOROLA
WARNING:
NOTE:
NOTE:
The state of TOV1 has no effect since there is no pin.
When TOVx is set, a TIM counter overflow takes precedence over a channel x
output compare if both occur at the same time.
Channel 1 should not be configured in input capture mode.
The user must configure TIM channel 1 in a mode other than input capture. It
is recommended that this procedure be part of the initialization of the system
after reset.
CHxMAX — Channel x Maximum Duty Cycle Bit
The PWM 0 percent duty cycle is defined as output low all of the time. To generate
the 0 percent duty cycle, select clear output on compare and then clear the TOVx
bit (CHxMAX = 0). The PWM 100 percent duty cycle is defined as output high all of
the time. To generate the 100 percent duty cycle, use the CHxMAX bit in the TSCx
register.
These read/write registers contain the captured TIM counter value of the input
capture function or the output compare value of the output compare function. The
state of the TIM channel registers after reset is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM
channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is
read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM
channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is
written.
PTBx/TCHx
When the TOVx bit is at 1 and clear output on compare is selected, setting the
CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to
100 percent. As
after it is set or cleared. The output stays at 100 percent duty cycle level until
the cycle after CHxMAX is cleared.
CHxMAX
Freescale Semiconductor, Inc.
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Timer Interface Module (TIM)
COMPARE
PERIOD
OUTPUT
Figure 11-9
Figure 11-9. CHxMAX Latency
OVERFLOW
shows, the CHxMAX bit takes effect in the cycle
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
Timer Interface Module (TIM)
COMPARE
OUTPUT
OVERFLOW
I/O Registers
Data Sheet
145