MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 129

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

10.6 SCI I/O Registers
10.6.1 SCI Data Register
MC68HC705C8A — Rev. 3
MOTOROLA
Address:
These I/O registers control and monitor SCI operation:
The SCI data register (SCDR) shown in
characters received and for characters transmitted.
Reset:
Read:
Write:
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Framing Errors — If the data recovery logic does not detect a logic
1 where the stop bit should be in an incoming character, it sets the
framing error (FE) bit in the SCSR. The FE bit is set at the same
time that the RDRF bit is set.
Receiver Interrupts — These sources can generate SCI receiver
interrupt requests:
– Receive Data Register Full (RDRF) — The RDRF bit in the
– Receiver Overrun (OR) — The OR bit in the SCSR indicates
– Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10
SCI data register (SCDR)
SCI control register 1 (SCCR1)
SCI control register 2 (SCCR2)
SCI status register (SCSR)
Serial Communications Interface (SCI)
$0011
Bit 7
Bit 7
SCSR indicates that the receive shift register has transferred a
character to the SCDR.
that the receive shift register shifted in a new character before
the previous character was read from the SCDR.
or 11 consecutive logic 1s shifted in from the PD0/RDI pin.
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Figure 10-5. SCI Data Register (SCDR)
Bit 6
6
Bit 5
5
Unaffected by reset
Bit 4
4
Serial Communications Interface (SCI)
Figure 10-5
Bit 3
3
Bit 2
2
is the buffer for
SCI I/O Registers
Bit 1
1
Technical Data
Bit 0
Bit 0