MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 81

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

7.4 Port B
7.4.1 Port B Data Register
MC68HC705C8A — Rev. 3
MOTOROLA
Address:
Port B is an 8-bit, general-purpose, bidirectional I/O port. Port B pins can
also be configured to function as external interrupts. The port B pullup
devices are enabled in mask option register 1 (MOR1). See
Option Register 1
The port B data register (PORTB) shown in
latch for each of the eight port B pins.
PB7–PB0 — Port B Data Bits
Reset:
Read:
Write:
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
Freescale Semiconductor, Inc.
For More Information On This Product,
$0001
Bit 7
PB7
Go to: www.freescale.com
Figure 7-4. Port B Data Register (PORTB)
Parallel Input/Output (I/O)
PB6
6
and
4.3.3 Port B
PB5
5
Unaffected by reset
PB4
4
Interrupts.
PB3
3
Figure 7-4
PB2
Parallel Input/Output (I/O)
2
contains a data
PB1
1
Technical Data
9.5.2 Mask
Bit 0
PB0
Port B