MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 131

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

10.6.3 SCI Control Register 2
MC68HC705C8A — Rev. 3
MOTOROLA
Address:
WAKE — Wakeup Bit
SCI control register 2 (SCCR2) shown in
functions:
TIE — Transmit Interrupt Enable Bit
Reset:
Read:
Write:
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition of the PD0/RDI pin. Reset has no effect
on the WAKE bit.
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•
•
•
•
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This read/write bit enables SCI interrupt requests when the TDRE bit
becomes set. Reset clears the TIE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Address mark wakeup
0 = Idle line wakeup
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
Enables the SCI receiver and SCI receiver interrupts
Enables the SCI transmitter and SCI transmitter interrupts
Enables SCI receiver idle interrupts
Enables SCI transmission complete interrupts
Enables SCI wakeup
Transmits SCI break characters
Serial Communications Interface (SCI)
$000F
Bit 7
TIE
0
Figure 10-7. SCI Control Register 2 (SCCR2)
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TCIE
6
0
RIE
5
0
ILIE
4
0
Serial Communications Interface (SCI)
Figure 10-7
TE
3
0
RE
2
0
has these
SCI I/O Registers
RWU
1
0
Technical Data
Bit 0
SBK
0