MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 145

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

11.5 Multiple-SPI Systems
MC68HC705C8A — Rev. 3
MOTOROLA
Example:
In a multiple-SPI system, all PD4/SCK pins are connected together, all
PD3/MOSI pins are connected together, and all PD2/MISO pins are
connected together.
Before a transmission, one SPI is configured as master and the rest are
configured as slaves.
master SPI and three slave SPIs.
Figure 11-5
three slave SPIs.
LDA #$1C
STA SPCR
LDA #$4C
STA SPCR
Freescale Semiconductor, Inc.
Figure 11-4. One Master and Three Slaves Block Diagram
For More Information On This Product,
MASTER MCU
Serial Peripheral Interface (SPI)
PD2/MISO
PD3/MOSI
PORT
Go to: www.freescale.com
PD4/SCK
is another block diagram with two master/slave SPIs and
I/O
PD5/SS
; MSTR = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
; SPI control register
; MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
; SPI control register
2
1
0
Figure 11-4
V
DD
SLAVE MCU 2
is a block diagram showing a single
SLAVE MCU 1
Serial Peripheral Interface (SPI)
SLAVE MCU 0
Multiple-SPI Systems
Technical Data