MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 67

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

5.3.4 Clock Monitor Reset
MC68HC705C8A — Rev. 3
MOTOROLA
NOTE:
The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
Figure 5-4
When the CME bit in the COP control register is set, the clock monitor
detects the absence of the internal bus clock for a certain period of time.
The timeout period depends on processing parameters and varies from
5 s to 100 s, which implies that systems using a bus clock rate of
200 kHz or less should not use the clock monitor function.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system for four bus cycles using
the bidirectional RESET pin.
Special consideration is required when using the STOP instruction with
the clock monitor. Since STOP causes the system clocks to halt, the
clock monitor issues a system reset when STOP is executed.
2. COP clear bit (COPC) at address $1FF0
Freescale Semiconductor, Inc.
NON-PROGRAMMABLE COP WATCHDOG (MC68HC05C4A TYPE)
For More Information On This Product,
Figure 5-4. Non-Programmable COP Watchdog Diagram
To clear the non-programmable COP watchdog and start a new
COP timeout period, write a logic 0 to bit 0 of address $1FF0.
Reading address $1FF0 returns the mask option register 1
(MOR1) data at that location. See
2
2
is a diagram of the non-programmable COP.
2
Go to: www.freescale.com
2
2
2
Resets
2
2
2
2
2
2
9.5.2 Mask Option Register
2
2
2
2
2
Reset Sources
Technical Data
NCOPE
Resets
1.