MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 65

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

MC68HC705C8A — Rev. 3
MOTOROLA
NOTE:
NOTE:
CME — Clock Monitor Enable Bit
Do not enable the clock monitor in applications with an internal clock
frequency of 200 kHz or less.
PCOPE — Programmable COP Enable Bit
Programming the non-programmable COP enable bit (NCOPE) in mask
option register 2 (MOR2) to logic 1 enables the non-programmable COP
watchdog. Setting the PCOPE bit while the NCOPE bit is programmed
to logic 1 enables both COP watchdogs to operate at the same time.
(See
CM1 and CM0 — COP Mode Bits
Bits 7–5 — Unused
This read/write bit enables the clock monitor. The clock monitor sets
the COPF bit and generates a reset if it detects an absent internal
clock for a period of from 5 s to 100 s. CME is readable and writable
at any time. Reset clears the CME bit.
If the clock monitor detects a slow clock, it drives the bidirectional
RESET pin low for four clock cycles. If the clock monitor detects an
absent clock, it drives the RESET pin low until the clock recovers.
This read/write bit enables the programmable COP watchdog.
PCOPE is readable at any time but can be written only once after
reset. Reset clears the PCOPE bit.
These read/write bits select the timeout period of the programmable
COP watchdog. (See
but can be written only once. They can be cleared only by reset.
Bits 7–5 always read as logic 0s. Reset clears bits 7–5.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Clock monitor enabled
0 = Clock monitor disabled
1 = Programmable COP watchdog enabled
0 = Programmable COP watchdog disabled
9.5.3 Mask Option Register
Go to: www.freescale.com
Resets
Table
5-1.) CM1 and CM0 can be read anytime
2.)
Reset Sources
Technical Data
Resets