MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 149

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

11.9.1 SPI Data Register
11.9.2 SPI Control Register
MC68HC705C8A — Rev. 3
MOTOROLA
Address:
Address:
The SPDR shown in
received by the SPI. Writing a byte to the SPDR places the byte directly
into the SPI shift register.
SPIE — SPI Interrupt Enable Bit
Reset:
Reset:
Read:
Read:
Write:
Write:
•
•
•
•
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SPI interrupts enabled
0 = SPI interrupts disabled
Enables SPI interrupt requests
Enables the SPI
Configures the SPI as master or slave
Selects serial clock polarity, phase, and frequency
$000C
$000A
SPIE
Bit 7
Bit 7
Bit 7
0
Serial Peripheral Interface (SPI)
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Figure 11-8. SPI Control Register (SPCR)
Figure 11-7. SPI Data Register (SPDR)
= Unimplemented
Bit 6
SPE
6
6
0
Figure 11-7
Bit 5
5
5
Unaffected by reset
MSTR
Bit 4
is the read buffer for characters
4
4
0
U = Unaffected
CPOL
Bit 3
U
3
3
Serial Peripheral Interface (SPI)
CPHA
Bit 2
U
2
2
SPI I/O Registers
SPR1
Bit 1
U
1
1
Technical Data
SPR0
Bit 0
Bit 0
Bit 0
U