MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 35

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

2.1 Contents
2.2 Introduction
2.3 Memory Map
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data — MC68HC705C8A
2.2
2.3
2.4
2.5
2.6
2.7
This section describes the organization of the on-chip memory.
The central processor unit (CPU) can address eight Kbytes of memory
and input/output (I/O) registers. The program counter typically advances
one address at a time through memory, reading the program instructions
and data. The programmable read-only memory (PROM) portion of
memory — either one-time programmable read-only memory
(OTPROM) or erasable, programmable read-only memory
(EPROM) — holds the program instructions, fixed data, user-defined
vectors, and interrupt service routines. The random-access memory
(RAM) portion of memory holds variable data.
I/O registers are memory-mapped so that the CPU can access their
locations in the same way that it accesses all other memory locations.
The shared stack area is used during processing of an interrupt or
Freescale Semiconductor, Inc.
For More Information On This Product,
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Memory
Section 2. Memory
Technical Data