MC68HC705C8ACFNE Freescale Semiconductor, MC68HC705C8ACFNE Datasheet - Page 39

• Manufacturer Part Number: MC68HC705C8ACFNE
• Description: IC MCU 8K 2.1MHZ OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• A/d Inputs: 4-Channel, 8-Bit
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: SCI/SPI
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part

MC68HC705C8A — Rev. 3
MOTOROLA
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Addr.
Port D Fixed Input Register
Port A Data Direction
Port B Data Direction
Port C Data Direction
Port C Data Register
Port A Data Register
Port B Data Register
Register (DDRA)
Register (DDRB)
Register Name
Unimplemented
Unimplemented
Unimplemented
See page 78.
See page 81.
See page 85.
See page 88.
See page 79.
See page 82.
See page 86.
(PORTB)
(PORTC)
(PORTD)
(PORTA)
(DDRC)
Figure 2-2. I/O Register Summary (Sheet 1 of 4)
Freescale Semiconductor, Inc.
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
For More Information On This Product,
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
DDRC7 DDRC6
DDRA7 DDRA6
DDRB7 DDRB6
Bit 7
PC7
PD7
PA7
PB7
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0
0
0
= Unimplemented
PB6
PC6
PA6
6
0
0
0
Memory
DDRA5
DDRB5
DDRC5
PB5
PC5
PA5
SS
5
0
0
0
U = Unaffected
DDRC4
DDRA4
DDRB4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
SCK
PB4
PC4
PA4
4
0
0
0
DDRA3
DDRB3
DDRC3
MOSI
PC3
PA3
PB3
3
0
0
0
DDRC2
DDRA2
DDRB2
MISO
PC2
PA2
PB2
2
0
0
0
Bootloader ROM
DDRA1
DDRB1
DDRC1 DDRC0
TDO
PC1
PA1
PB1
Technical Data
1
0
0
0
Memory
DDRA0
DDRB0
Bit 0
PC0
PA0
PB0
RDI
0
0
0