PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 102

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
8.3
The external memory interface implemented in
PIC18F8410 devices operates only in 8-Bit Multiplexed
mode; data shares the 8 Least Significant bits of the
address bus.
Figure 8-1
mode for PIC18F8410 devices. This mode is used for
a single 8-bit memory connected for 16-bit operation.
The instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequen-
tially fetched within one instruction cycle (T
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 T
ory speed selection, glue logic propagation delay times
must be considered along with setup and hold times.
FIGURE 8-7:
DS39635C-page 102
CY
(2 times the instruction rate). For proper mem-
8-Bit Mode
shows an example of 8-Bit Multiplexed
Note 1:
PIC18F8410
2:
8-BIT MULTIPLEXED MODE EXAMPLE
AD<15:8>
A<19:16>
Upper order address bits are used only for 20-bit address width. The upper AD byte is
used for all address widths except 8-bit.
This signal only applies to table writes. See
Writes”.
AD<7:0>
WRL
ALE
BA0
CE
OE
CY
).
373
The Address Latch Enable (ALE) pin indicates that the
address bits, A<15:0>, are available on the external
memory interface bus. The Output Enable signal (OE)
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing; it is inactive
(asserted high) whenever the device is in Sleep mode.
This generally includes basic EPROM and Flash devices.
It allows table writes to byte-wide external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD<15:0> bus. The appropriate level of the BA0 control
line is strobed on the LSb of the TBLPTR.
Section 7.1 “Table Reads and Table
D<7:0>
A<19:0>
D<15:8>
Address Bus
Data Bus
Control Lines
 2010 Microchip Technology Inc.
A0
A<x:1>
D<7:0>
CE
OE
WR
(2)