PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 336

IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC

PIC18LF6310T-I/PT

Manufacturer Part Number
PIC18LF6310T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets

Specifications of PIC18LF6310T-I/PT

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF6310T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6310/6410/8310/8410
TBLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
DS39635C-page 336
Table Write
TBLWT ( *; *+; *-; +*)
None
if TBLWT*,
(TABLAT)  Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT)  Holding Register,
(TBLPTR) + 1  TBLPTR;
if TBLWT*-,
(TABLAT)  Holding Register,
(TBLPTR) – 1  TBLPTR;
if TBLWT+*,
(TBLPTR) + 1  TBLPTR,
(TABLAT)  Holding Register
None
This instruction uses the 3 LSBs of
TBLPTR to determine which of the 8
holding registers the TABLAT is written to.
The holding registers are used to program
the contents of Program Memory (P.M.).
(Refer to
for additional details on programming Flash
memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
1
2
operation
Decode
0000
Q1
No
TBLPTR[0] = 0: Least Significant
TBLPTR[0] = 1: Most Significant
Section 7.0 “Program Memory”
operation
operation
TABLAT)
(Read
0000
Q2
No
No
operation
operation
0000
Byte of Program
Memory Word
Byte of Program
Memory Word
Q3
No
No
nn=0 *
Register )
operation
operation
(Write to
Holding
=1 *+
=2 *-
=3 +*
11nn
Q4
No
No
TBLWT
Example 1:
Example 2:
Note:
Before Instruction
After Instructions (table write completion)
Before Instruction
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
The TBLWT instruction is not available in
PIC18F6310/6410 devices (i.e., 64-pin
devices) in normal operating modes.
TBLWT
PIC18F8310/8410
external memory interface and only when
writing to an external memory device.
For more information, refer to
“Writing to Program Memory Space
(PIC18F8310/8410
Section 7.6
On-Chip
Mode)”.
Table Write (Continued)
TBLWT *+;
TBLWT +*;
can
Program
 2010 Microchip Technology Inc.
“Writing
only
=
=
=
=
=
=
=
=
=
=
=
=
=
=
devices
Memory
55h
00A356h
FFh
55h
00A357h
55h
34h
01389Ah
FFh
FFh
34h
01389Bh
FFh
34h
be
only)”
and
Section 7.4
used
with
Erasing
(ICSP
and
the
by

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