PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 105

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory
operations.
TABLE 8-2:
 2010 Microchip Technology Inc.
MEMCON
CONFIG3L
CONFIG3H
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the external memory interface.
Name
Operation in Power-Managed
Modes
MCLRE
EBDIS
WAIT
Bit 7
REGISTERS ASSOCIATED WITH THE EXTERNAL MEMORY INTERFACE
Bit 6
BW
—
—
WAIT1
Bit 5
—
—
PIC18F6310/6410/8310/8410
WAIT0
Bit 4
—
—
Bit 3
—
—
—
If operations in a lower power Run mode are antici-
pated, users should provide in their applications for
adjusting memory access times at the lower clock
speeds.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are sus-
pended. The state of the external bus is frozen with the
address/data pins and most of the control pins holding
at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins which are held at logic high.
LPT1OSC
Bit 2
—
—
WM1
Bit 1
PM1
—
CCP2MX
DS39635C-page 105
WM0
Bit 0
PM0
on Page
Values
Reset
285
286
65