PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 185

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.8
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
In most power-managed modes, a clock is provided to
the peripherals. That clock should be from the primary
clock source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See
“Clock Sources and Oscillator Switching”
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
TABLE 17-2:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON1
SSPSTAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Name
SLEEP OPERATION
PORTC Data Direction Register
PORTF Data Direction Register
Master Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
WCOL
PSPIF
PSPIE
PSPIP
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
SSPEN
RC1IE
RC1IP
RC1IF
Bit 5
D/A
Section 3.7
PIC18F6310/6410/8310/8410
INT0IE
TX1IE
TX1IP
TX1IF
for
Bit 4
CKP
P
SSPM3
SSPIE
SSPIP
SSPIF
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10
Table 17-1
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also an SMP bit which controls when the data
is sampled.
RBIE
Bit 3
Standard SPI Mode
S
Terminology
0, 0
0, 1
1, 0
1, 1
TMR0IF
CCP1IF
CCP1IE
CCP1IP
SSPM2
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 2
R/W
shows the compatibility between the
SPI BUS MODES
TMR2IF
TMR2IE
TMR2IP
SSPM1
INT0IF
Bit 1
UA
CKP
Control Bits State
0
0
1
1
TMR1IF
TMR1IE
TMR1IP
SSPM0
RBIF
Bit 0
DS39635C-page 185
BF
CKE
on Page
Values
Reset
1
0
1
0
63
65
65
65
66
66
64
64
64