PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 406

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
RESET ............................................................................. 327
Reset .................................................................................. 55
Resets .............................................................................. 281
RETFIE ............................................................................ 328
RETLW ............................................................................. 328
RETURN .......................................................................... 329
Return Address Stack ........................................................ 70
Return Stack Pointer (STKPTR) ........................................ 71
Revision History ............................................................... 395
RLCF ................................................................................ 329
RLNCF ............................................................................. 330
RRCF ............................................................................... 330
RRNCF ............................................................................. 331
Run Modes
DS39635C-page 406
HLVDCON (HLVD Control) ...................................... 275
INTCON (Interrupt Control) ...................................... 111
INTCON2 (Interrupt Control 2) ................................. 112
INTCON3 (Interrupt Control 3) ................................. 113
IPR1 (Peripheral Interrupt Priority 1) ........................ 120
IPR2 (Peripheral Interrupt Priority 2) ........................ 121
IPR3 (Peripheral Interrupt Priority 3) ........................ 122
MEMCON (Memory Control) ...................................... 95
OSCCON (Oscillator Control) .................................... 42
OSCTUNE (Oscillator Tuning) ................................... 39
PIE1 (Peripheral Interrupt Enable 1) ........................ 117
PIE2 (Peripheral Interrupt Enable 2) ........................ 118
PIE3 (Peripheral Interrupt Enable 3) ........................ 119
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 114
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 115
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 116
PSPCON (Parallel Slave Port Control) .................... 149
RCON (Reset Control) ....................................... 56, 123
RCSTA2 (AUSART2 Receive Status
SSPCON1 (MSSP Control 1, SPI Mode) ................. 179
SSPCON2, (I
SSPSTAT (MSSP Status, I
SSPSTAT (MSSP Status, SPI Mode) .............. 178, 219
T0CON (Timer0 Control) .......................................... 151
T1CON (Timer1 Control) .......................................... 155
T2CON (Timer2 Control) .......................................... 161
T3CON (Timer3 Control) .......................................... 163
TXSTA1 (EUSART1 Transmit Status
TXSTA2 (AUSART2 Transmit Status
WDTCON (Watchdog Timer Control) ....................... 291
MCLR Reset, Normal Operation ................................ 55
MCLR Reset, Power Managed Modes ...................... 55
Power-on Reset (POR) .............................................. 55
Programmable Brown-out Reset (BOR) .................... 55
RESET Instruction ..................................................... 55
Stack Full Reset ......................................................... 55
Stack Underflow Reset .............................................. 55
Watchdog Timer (WDT) Reset ................................... 55
PRI_RUN ................................................................... 46
RC_RUN .................................................................... 48
SEC_RUN .................................................................. 46
and Control) ..................................................... 243
and Control) ..................................................... 218
and Control) ..................................................... 242
2
C Mode) ............................................ 189
2
C Mode) ............... 187, 188
S
SCK ................................................................................. 177
SDI ................................................................................... 177
SDO ................................................................................. 177
Serial Clock, SCK ............................................................ 177
Serial Data In (SDI) .......................................................... 177
Serial Data Out (SDO) ..................................................... 177
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 331
Slave Select (SS) ............................................................. 177
SLEEP ............................................................................. 332
Sleep Mode
Software Simulator (MPLAB SIM) ................................... 349
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 281
Special Function Registers ................................................ 78
SPI Mode (MSSP)
SS .................................................................................... 177
SSPOV ............................................................................ 207
SSPOV Status Flag ......................................................... 207
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 72
Standard Instructions ....................................................... 297
SUBFSR .......................................................................... 343
SUBFWB ......................................................................... 332
SUBLW ............................................................................ 333
SUBULNK ........................................................................ 343
SUBWF ............................................................................ 333
SUBWFB ......................................................................... 334
SWAPF ............................................................................ 334
T
T0CON Register
Table Pointer Operations (table) ........................................ 90
Table Reads/Table Writes ................................................. 72
TBLRD ............................................................................. 335
TBLWT ............................................................................. 336
Time-out in Various Situations (table) ................................ 59
OSC1 and OSC2 Pin States ...................................... 43
Map ............................................................................ 78
Associated Registers ............................................... 185
Bus Mode Compatibility ........................................... 185
Effects of a Reset .................................................... 185
Enabling SPI I/O ...................................................... 181
Master Mode ............................................................ 182
Master/Slave Connection ......................................... 181
Operation ................................................................. 180
Serial Clock .............................................................. 177
Serial Data In ........................................................... 177
Serial Data Out ........................................................ 177
Slave Mode .............................................................. 183
Slave Select ............................................................. 177
Slave Select Synchronization .................................. 183
Sleep Operation ....................................................... 185
SPI Clock ................................................................. 182
Typical Connection .................................................. 181
R/W Bit ............................................................ 190, 191
PSA Bit .................................................................... 153
T0CS Bit .................................................................. 152
T0PS2:T0PS0 Bits ................................................... 153
T0SE Bit .................................................................. 152
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