PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 264

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
20.8
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
TABLE 20-2:
DS39635C-page 264
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTF
TRISF
LATF
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
Use of the CCP2 Trigger
These pins may be configured as port pins depending on the oscillator mode selected.
PORTF Data Direction Register
LATF Output Latch Register
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
TRISA7
OSCFIF
OSCFIE
OSCFIP
PSPIF
PSPIE
PSPIP
ADFM
RA7
Bit 7
RF7
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
TRISA6
RA6
CMIE
CMIP
CMIF
ADIF
ADIE
ADIP
Bit 6
RF6
—
—
—
(1)
(1)
PORTA Data Direction Register
VCFG1
ACQT2
RC1IE
RC1IP
RC1IF
CHS3
Bit 5
RA5
RF5
—
—
—
VCFG0
ACQT1
INT0IE
TX1IE
TX1IP
TX1IF
CHS2
Bit 4
RA4
RF4
—
—
—
PCFG3
ACQT0
SSPIF
SSPIE
SSPIP
BCLIE
BCLIP
BCLIF
CHS1
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
the “Special Event Trigger” sets the GO/DONE bit
(starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
RBIE
Bit 3
RA3
RF3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
PCFG2
ADCS2
CHS0
Bit 2
RA2
RF2
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
PCFG1
ADCS1
INT0IF
Bit 1
 2010 Microchip Technology Inc.
RA1
RF1
ACQ
time selected before
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
RF0
on Page
Values
Reset
63
65
65
65
65
65
65
64
64
64
64
64
66
66
66
66
66