PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 244

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
19.1
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, BRGH bit
(TXSTA<2>) also controls the baud rate. In Synchro-
nous mode, BRGH is ignored.
formula for computation of the baud rate for different
AUSART modes, which only apply in Master mode
(internally generated clock).
Given the desired baud rate and F
integer value for the SPBRG2 register can be calcu-
lated using the formulas in
error in baud rate can be determined. An example
calculation is shown in
rates and error values for the various Asynchronous
modes are shown in
geous to use the high baud rate (BRGH = 1) to reduce
the baud rate error, or achieve a slow baud rate for a
fast oscillator frequency.
TABLE 19-1:
EXAMPLE 19-1:
TABLE 19-2:
DS39635C-page 244
Legend: x = Don’t care, n = Value of SPBRG2 register
TXSTA2
RCSTA2
SPBRG2
Legend: Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRG2:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Name
SYNC
Configuration Bits
0
0
1
AUSART Baud Rate Generator
(BRG)
AUSART2 Baud Rate Generator Register
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
X = ((F
OSC
BRGH
Table
CALCULATING BAUD RATE ERROR
= F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
0
1
x
Example
Table
OSC
19-2. It may be advanta-
Bit 6
OSC
TX9
RX9
/(64 ([SPBRG2] + 1))
Table 19-1
/Desired Baud Rate)/64) – 1
19-1. From this, the
19-1. Typical baud
OSC
SREN
TXEN
Bit 5
, the nearest
BRG/AUSART Mode
shows the
Asynchronous
Asynchronous
Synchronous
CREN
SYNC
Bit 4
ADDEN
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
19.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
19.1.2
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX2 pin.
Bit 3
—
BRGH
FERR
Bit 2
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
Baud Rate Formula
Bit 1
 2010 Microchip Technology Inc.
F
F
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
RX9D
TX9D
Bit 0
Values on
Reset
Page
66
66
66