PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 210

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
17.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode
17.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
FIGURE 17-24:
DS39635C-page 210
Note: T
Note: T
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCL
SDA
Write to SSPCON2,
Sequence
SSPIF
BRG
BRG
Falling edge of
9th clock
Acknowledge sequence starts here,
SDA
SCL
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
set PEN
Set SSPIF at the end
of receive
BRG
ACKEN = 1, ACKDT = 0
Enable
. The SCL pin is then
write to SSPCON2
T
T
(Figure
BRG
BRG
bit,
SDA asserted low before rising edge of clock
to setup Stop condition
8
D0
ACKEN
17-23).
T
SCL brought high after T
BRG
BRG
)
Cleared in
software
P
T
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
BRG
T
BRG
ACK
transmit, the SCL line is held low after the falling edge of
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
the ninth clock. When the PEN bit is set, the master will
assert the SDA line low. When the SDA line is sampled
low, the Baud Rate Generator is reloaded and counts
down to ‘0’. When the Baud Rate Generator times out,
the SCL pin will be brought high and one T
Rate Generator rollover count) later, the SDA pin will be
deasserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A T
the PEN bit is cleared and the SSPIF bit is set
(Figure
17.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
PEN bit (SSPCON2<2>) is cleared by
T
hardware and the SSPIF bit is set
BRG
9
BRG
Set SSPIF at the end
of Acknowledge sequence
17-24).
BRG
, followed by SDA = 1 for T
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
 2010 Microchip Technology Inc.
Cleared in
software
BRG
BRG
BRG
(Baud
later,