PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 81

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 6-3:
 2010 Microchip Technology Inc.
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
6:
(2)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
INTOSC
The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
EUSART1 Baud Rate Generator Low Byte
EUSART1 Receive Register
EUSART1 Transmit Register
PORTJ Data Direction Register
PORTH Data Direction Register
PORTF Data Direction Register
PORTE Data Direction Register
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
LATJ Output Latch Register
LATH Output Latch Register
LATF Output Latch Register
LATE Output Latch Register
LATD Output Latch Register
LATC Output Latch Register
LATB Output Latch Register
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
TRISA7
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
PSPIP
PSPIF
PSPIE
EBDIS
RA7
CSRC
SPEN
Bit 7
—
—
—
—
—
—
(5)
REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
(5)
Modes”.
(5)
TRISA6
PLLEN
LATA6
RA6
CMIP
CMIE
CMIF
ADIP
ADIF
ADIE
Bit 6
RX9
TX9
—
—
—
—
—
—
—
(5)
(5)
(3)
(5)
PORTA Data Direction Register
LATA Output Latch Register
Read PORTA pins, Write PORTA Data Latch
RC2IP
RC2IE
RC1IP
RC1IE
WAIT1
RG5
SREN
RC2IF
RC1IF
TXEN
(BOR)”.
Bit 5
—
—
—
—
—
—
(4)
PORTG Data Direction Register
LATG Output Latch Register
Read PORTG pins<4:0>, Write PORTG Data Latch<4:0>
PIC18F6310/6410/8310/8410
WAIT0
SYNC
CREN
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
TUN4
Bit 4
—
—
—
SENDB
ADDEN
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
Bit 3
—
—
—
—
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
BRGH
FERR
TUN2
Bit 2
—
—
—
—
TMR3IP
TMR3IE
TMR2IP
TMR2IE
TMR3IF
TMR2IF
OERR
TRMT
TUN1
WM1
Bit 1
—
—
—
CCP3IP
CCP3IE
CCP2IP
CCP2IE
TMR1IP
TMR1IF
TMR1IE
CCP3IF
CCP2IF
TX9D
RX9D
TUN0
WM0
Bit 0
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
--11 ---1
--00 ---0
--00 ---0
11-- 1111
00-- 0000
00-- 0000
1111 1111
0000 0000
0000 0000
0-00 --00
00-0 0000
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
Section 3.6.4 “PLL in
POR, BOR
DS39635C-page 81
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