PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 143

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 11-13: PORTG FUNCTIONS
TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
 2010 Microchip Technology Inc.
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3
RG4
RG5/MCLR/V
Legend:
Note 1:
PORTG
LATG
TRISG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
Pin Name
Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RG5 does not have a corresponding TRISG bit.
RG5 is available as an input only when MCLR is disabled.
PP
Function
MCLR
CCP3
RG0
RG2
RG3
RG4
RG5
CK2
RX2
DT2
R21
TX2
V
Bit 7
PP
—
—
—
Setting
TRIS
—
Bit 6
—
—
0
1
0
1
0
1
1
1
1
0
1
1
1
1
0
1
0
1
—
—
—
(1)
I/O
O
O
O
O
O
O
O
O
O
RG5
I
I
I
I
I
I
I
I
I
I
I
I
Bit 5
—
—
PIC18F6310/6410/8310/8410
(1)
Type
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATG Output Latch Register
PORTG Data Direction Register
Bit 4
RG4
LATG<0> data output.
PORTG<0> data input.
CCP3 compare and PWM output; takes priority over port data.
CCP3 capture input.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial data output (AUSART module); takes priority over
port data.
Synchronous serial data input (AUSART module). User must
configure as an input.
Synchronous serial clock input (AUSART module).
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (AUSART module).
Synchronous serial data output (AUSART module); takes priority over
port data.
Synchronous serial data input (AUSART module). User must
configure as an input.
LATG<3> data output.
PORTG<3> data input.
LATG<4> data output.
PORTG<4> data input.
PORTG<5> data input; enabled when MCLRE Configuration bit is
clear.
External Master Clear input; enabled when MCLRE Configuration bit is
set.
High-Voltage Detection; used for ICSP™ mode entry detection.
Always available, regardless of pin mode.
Bit 3
RG3
Bit 2
RG2
Description
Bit 1
RG1
Bit 0
RG0
DS39635C-page 143
Values on
Reset
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