PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 82

IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC

PIC18LF6310T-I/PT

Manufacturer Part Number
PIC18LF6310T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets

Specifications of PIC18LF6310T-I/PT

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF6310T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6310/6410/8310/8410
TABLE 6-3:
DS39635C-page 82
SPBRGH1
BAUDCON1
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
INTOSC
The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
EUSART1 Baud Rate Generator High Byte
AUSART2 Baud Rate Generator
AUSART2 Receive Register
AUSART2 Transmit Register
ABDOVF
CSRC
SPEN
Bit 7
REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
Modes”.
RCIDL
Bit 6
TX9
RX9
RXDTP
SREN
TXEN
(BOR)”.
Bit 5
TXCKP
SYNC
CREN
Bit 4
ADDEN
BRG16
Bit 3
BRGH
FERR
Bit 2
OERR
TRMT
WUE
Bit 1
 2010 Microchip Technology Inc.
ABDEN
RX9D
TX9D
Bit 0
0000 0000
0100 0-00
0000 0000
0000 0000
xxxx xxxx
0000 -010
0000 000x
POR, BOR
Section 3.6.4 “PLL in
Value on
on page:
Details
66, 221
66, 220
66, 234
66, 248
66, 246
66, 242
66, 243

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