PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 292

• Manufacturer Part Number: PIC18LF6310T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
24.3
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is LP, XT, HS or HSPLL
(Crystal-Based modes). Other sources do not require a
OST start-up delay; for these, Two-Speed Start-up
should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
To use a higher clock speed on wake-up, the INTOSC or
postscaler clock sources can be selected to provide a
higher clock speed by setting bits, IRCF<2:0>, immedi-
ately after Reset. For wake-ups from Sleep, the INTOSC
or postscaler clock sources can be selected by setting
the IRCF<2:0> bits prior to entering Sleep mode.
FIGURE 24-2:
DS39635C-page 292
Two-Speed Start-up
Note 1: T
CPU Clock
Multiplexer
PLL Clock
Peripheral
Program
INTOSC
Counter
Output
OSC1
Clock
Wake from Interrupt Event
OST
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
= 1024 T
PC
OSC
; T
Q1
PLL
T
OST (1)
= 2 ms (approx). These intervals are not shown to scale.
Q2
PC + 2
T
OSTS bit Set
Q3
PLL
(1)
Q4
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
24.3.1
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including
Section 4.1.2 “Entering Power-Managed
In practice, this means that user code can change
the
instructions before the OST times out. This would
allow an application to briefly wake-up, perform
routine “housekeeping” tasks and return to Sleep
before the device starts to operate from the primary
oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
Q1
1
Transition
2
SCS<1:0>
Clock
n-1 n
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
serial
PC + 4
bits
SLEEP
Q2
 2010 Microchip Technology Inc.
Q3 Q4
setting
instructions
Q1
PC + 6
or
Q2
Q3
issue
(refer
Modes”).
SLEEP
to