MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 103

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Table 4-3
Table 4-4
invalidate all bit (CACR[CINV]).
Freescale Semiconductor
DBWE
EUSP
CLNF
Field
DCM
DWP
7–6
3–2
1–0
9
8
5
4
[CENB]
Default cache mode. This bit defines the default cache mode. For more information on the selection of the effective
memory attributes, see
0 Caching enabled
1 Caching disabled
Default buffered write enable. This bit defines the default value for enabling buffered writes. If DBWE = 0, the
termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is
completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in the
bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and
the external bus. Generally, enabled buffered writes provide higher system performance but recovery from access
errors can be more difficult. For the ColdFire core, reporting access errors on operand writes is always imprecise
and enabling buffered writes further decouples the write instruction and the signaling of the fault
0 Disable buffered writes
1 Enable buffered writes
Reserved, must be cleared.
Default write protection
0 Read and write accesses permitted
1 Only read accesses permitted
Enable user stack pointer. See
information on the dual stack pointer implementation.
0 Disable the processor’s use of the User Stack Pointer
1 Enable the processor’s use of the User Stack Pointer
Reserved, must be cleared.
Cache line fill. These bits control the size of the memory request the cache issues to the bus controller for different
initial instruction line access offsets. See
shows the relationship between CACR[CENB, DISI, & DISD] bits and the cache configuration.
shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache
CACR
0
1
1
1
CACR
[DISI]
0
0
1
x
[DISD]
CACR
Table 4-3. Cache Configuration as Defined by CACR
x
0
1
0
Table 4-2. CACR Field Descriptions (continued)
Section 4.3.2, “Memory Reference
Instruction Cache
Split Instruction/
Section 2.2.3, “Supervisor/User Stack Pointers (A7 and
Configuration
Data Cache
Data Cache
N/A
Table 4-6
1 KByte direct-mapped instruction cache (uses upper
half of tag and storage arrays) and 1 KByte
direct-mapped write-through data cache (uses lower
half of tag and storage arrays)
2 KByte direct-mapped instruction cache (uses all of
tag and storage arrays)
(uses all of tag and storage arrays)
Cache is completely disabled
2 KByte direct-mapped write-through data cache
Description
for external fetch size based on miss address and CLNF.
Attributes.
Description
OTHER_A7)”for more
Cache
4-5