MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 740
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Revision History
B-4
Table 33-13 on page
Table 33-15 on page
Table 25-12 on page
Figure 32-1 on page
Table 33-15 on page
Figure 33-3 on page
Figure 33-4 on page
Figure 33-5 on page
Table 33-16 on page
Table 33-17 on page
Table 33-17 on page
Table 28-4 on page
Table 28-5 on page
Table 32-1 on page
Table 33-1 on page
27.6.2/27-8
Location
30.1/30-1
25-22
28-10
28-11
33-11
33-12
33-12
33-14
33-15
33-16
33-17
33-18
33-18
32-2
32-4
33-1
Changed equation in PRES_DIV field description to the following:
Added “Note:
of the external reset configuration.”
Changed equation in QPR field description to the following:
Multiplied all f
Added “Note: Enabling Flash security will disable BDM communications.”
Replaced “SCKE” with “SCKE.”
Replaced “PEL2” with “PEL6, ” “PNQ6” with “PNQ7,” “PNQ5” with “PNQ6,” “PEL5” with “PEL1,” “PNQ4”
with “PNQ5,” “PNQ3” with “PNQ4,” “PNQ2” with “PNQ3,” “PNQ1” with “PNQ2,” “PNQ0” with “PNQ1,”
“PQS0” with “PQS1,” “PQS1” with “PQS0,” “PJ6” with “PJ7,” “RAS0” with “SDRAM_CS0,” “RAS1” with
“SDRAM_CS1,” and “SCKE” with “SCKE.”
Changed value for “ESD Target for Human Body Model” to “2000” and “ESD Target for Machine Model”
to “200.”
Changed value in “Maximum number of guaranteed program/erase cycles before failure” row to “10,000.”
Changed the max value in specs B6a–B6c to “0.5t
Changed the min value in spec B7a to “0.5t
and
Changed the min value in spec D8 to “2” and the max value to”'—”.
Changed the max value in spec G1a to “12.”
Added the following footnote: “Because of long delays associated with the PQA/PQB pads, signals on the
PQA/PQB pins will be updated on the following edge of the clock.”
Figure
Table B-2. Rev. 0.1 to Rev. 1 Changes (continued)
33-5.
SYS
When Flash security is enabled, the chip will boot in single chip mode regardless
divisor values in this table by 2.
S-clock
f
QCLK
CYC
=
Description
=
+ 2” and reflected the change in
2(QPR[6:0] + 1)
-------------------------------------------- -
2 PRESDIV + 1
(
CYC
f
+ 10.”
f
SYS
SYS
)
Figure
Freescale Semiconductor
33-3,
Figure
33-4,
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