MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 234

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

External Interface Module (EIM)
13.4.7
The processor can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it
is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst cycle. A line
transfer to a 32-bit port would take a 4-longword burst cycle.
The external bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize DMA
transfers. A user can add wait states by delaying termination of the cycle. The initiation of a burst cycle is
encoded on the size pins. For burst transfers to smaller port sizes, SIZ[1:0] indicates the size of the entire
transfer. For example, if the processor writes a longword to an 8-bit port, SIZ[1:0] = 00 for the first byte
transfer and does not change.
The CSCRs can be used to enable bursting for reads, writes, or both. Processor memory space can be
declared burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW]. A line
access to a burst-inhibited region first accesses the processor bus encoded as a line access. The SIZ[1:0]
encoding does not exceed the programmed port size. The address changes if internal termination is used
but does not change if external termination is used, as shown in
13.4.7.1 Line Transfers
A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the
aligned address; therefore, the bus interface supports line transfers on multiple address boundaries.
Table 13-4
13.4.7.2 Line Read Bus Cycles
Figure 13-12
read bus cycle with the first data transfer sampled on the rising edge of S4, but the next pipelined burst
data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined data burst is single cycle
until the last one, which can be held for up to two CLKOUT cycles after TA is asserted. Note that CSn are
asserted throughout the burst transfer. This example shows the timing for external termination, which
differs from the internal termination example in
the beginning (assertion of TS and TIP) and end (negation of TIP) of the transfer.
13-10
Burst Cycles
shows allowable patterns for line accesses.
and
Figure 13-13
Table 13-4. Allowable Line Access Patterns
show a line access read with zero wait states. The access starts like a basic
A[3:2]
00
01
10
11
Figure 13-13
Longword Accesses
only in that the address lines change only at
0–4–8–C
4–8–C–0
8–C–0–4
C–0–4–8
Figure 13-12
and
Figure
Freescale Semiconductor
13-13.