MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 634
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Debug Support
30.5
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial command
interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module.
Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM
commands, such as memory accesses, can be executed while the processor is running.
30.5.1
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation
requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of
priority:
30-16
28–22/
20–18/
28/12
27/11
26/10
12–6
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
Bits
4–2
Background Debug Mode (BDM)
CPU Halt
Name
EPC
EDx
EAx
PCI
DI
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW
EDWL
EDWU Upper data word.
EDLL
EDLM
EDUM
EDUU
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the DBR
contents.
Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the breakpoint.
EAI
EAR
EAL
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR and PBMR
to enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and
PBMR.
Data longword. Entire processor’s local data bus.
Lower data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR
and ABHR.
Enable address breakpoint range. The breakpoint is based on the inclusive range defined
by ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the ABLR.
Table 30-14. TDR Field Descriptions (continued)
Description
Freescale Semiconductor
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