MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 497

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

25.5.9
IMASK contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer will
generate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAG bit
is set).
Freescale Semiconductor
Bits
5–4
8
7
6
3
2
1
0
Interrupt Mask Register (IMASK)
WAKEINT Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
RXWARN
BOFFINT
ERRINT
TX/RX
Name
IDLE
FCS
—
Receiver error status flag. The RXWARN status flag reflects the status of the FlexCAN
receive error counter.
0 Receive error counter < 96.
1 Receive error counter ≥ 96.
Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 The CAN bus is not idle.
1 The CAN bus is idle.
Transmit/receive status. The TX/RX bit indicates when the FlexCAN module is transmitting
or receiving a message. TX/RX has no meaning when IDLE = 1.
0 The FlexCAN is receiving a message if IDLE = 0.
1 The FlexCAN is transmitting a message if IDLE = 0.
Fault confinement state. The FCS[1:0] field describes the state of the FlexCAN. If the
SOFTRST bit in CANMCR is asserted while the FlexCAN is in the bus off state, the error and
status register is reset, including FCS[1:0]. However, as soon as the FlexCAN exits reset,
FCS[1:0] bits will again reflect the bus off state. Refer to
Error Counter
confinement states.
00 Error active
01 Error passive
1X Reserved
Reserved, should be cleared.
Bus off interrupt. The BOFFINT bit is used to request an interrupt when the FlexCAN enters
the bus off state. To clear this bit, first read it as a one, then write a one. Writing zero has no
effect.
0 No bus off interrupt requested.
1 When the FlexCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in
Error interrupt. The ERRINT bit is used to request an interrupt when the FlexCAN detects a
transmit or receive error. To clear this bit, first read it as a one, then write a one. Writing zero
has no effect.
0 No error interrupt request.
1 If an event which causes one of the error bits in the error and status register to be set
FlexCAN module is in low-power stop mode. To clear this bit, first read it as a one, then write
a one. Writing zero has no effect.
0 No wake interrupt requested.
1 When the FlexCAN is in low-power stop mode and a recessive to dominant transition is
CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after
reset.
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an
interrupt request is generated.
Table 25-17. ESTAT Field Descriptions (continued)
(RXECTR)” for more information on entry into and exit from the various fault
Description
Section 25.5.11, “FlexCAN Receive
FlexCAN
25-27