MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 210

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Edge Port Module (EPORT)
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be
configured to exit the low-power modes by generating an interrupt request on either a selected edge or a
low level on an external pin. In stop mode, there are no clocks available to perform the edge-detect
function. Only the level-detect logic is active (if configured) to allow any low level on the external
interrupt pin to generate an interrupt (if enabled) to exit stop mode.
11.3
All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of
CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect
logic are also synchronized to the rising edge of CLKOUT. These pins use Schmitt triggered input buffers
which have built in hysteresis designed to decrease the probability of generating false edge-triggered
interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding
bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset.
11-2
Low-power Mode
Interrupt/General-Purpose I/O Pin Descriptions
Doze
Wait
Stop
The input pin synchronizer is bypassed for the level-detect logic since no
clocks are available.
Table 11-1. Edge Port Module Operation in Low-power Modes
EPORT Operation
Level-sensing Only
Normal
Normal
NOTE
Any IRQx Interrupt at or above level in LPICR
Any IRQx Interrupt at or above level in LPICR
Any IRQx Interrupt set for level-sensing at or
above level in LPICR
Mode Exit
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