MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 163

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee that
the programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities.
8.6
This section details the functionality of the System Access Control Unit (SACU) which provides the
mechanism needed to implement secure bus transactions to the address space mapped to the internal
modules.
8.6.1
The SACU supports the traditional model of two privilege levels: supervisor and user. Typically, memory
references with the supervisor attribute have total accessibility to all the resources in the system, while user
mode references cannot access system control and configuration registers. In many systems, the operating
system executes in supervisor mode, while application software executes in user mode.
The SACU further partitions the access control functions into two parts: one control register defines the
privilege level associated with each bus master, and another set of control registers define the access levels
associated with the peripheral modules and the memory space.
The SACU’s programming model is physically implemented as part of the System Control Module (SCM)
with the actual access control logic included as part of the arbitration controller. Each bus transaction
targeted for the IPS space is first checked to see if its privilege rights allow access to the given memory
space. If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are
insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an
exception, and the targeted module not accessed.
Freescale Semiconductor
11–8
Bits
7–0
14
13
12
System Access Control Unit (SACU)
Overview
LCKOUT_TIME Lock-out Time. Lock-out time for a master being denied the bus.
TIMEOUT
PRKLAST
The M1_PRTY field should not be set for a priority higher than third
(default).
FIXED
Name
—
Fixed or round robin arbitration
0 round robin arbitration
1 fixed arbitration
Timeout Enable
0 disable count for when a master is locked out by other masters.
1 enable count for when a master is locked out by other masters and allow access when
Park on the last active master or highest priority master if no masters are active
0 park on last active master
1 park on highest priority master
The lock out time is defined as 2^ LCKOUT_TIME[3:0].
Reserved, should be cleared.
LCKOUT_TIME is reached.
Table 8-6. MPARK Field Description (continued)
NOTE
Description
System Control Module (SCM)
8-11