MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 382

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

General Purpose Timer Modules (GPTA and GPTB)
20.5.15 Pulse Accumulator Control Register (GPTPACTL)
20-14
Bit(s)
3–2
7
6
5
4
Address
Reset
Field
R/W
PAMOD
PEDGE
Name
CLK
PAE
—
Figure 20-17. Pulse Accumulator Control Register (GPTPACTL)
—
7
Reserved, should be cleared.
Enables the pulse accumulator.
1 Pulse accumulator enabled
0 Pulse accumulator disabled
Note: The pulse accumulator can operate in event mode even when the GPT enable
bit, GPTEN, is clear.
Pulse accumulator mode. Selects event counter mode or gated time accumulation
mode.
1 Gated time accumulation mode
0 Event counter mode
Pulse accumulator edge. Selects falling or rising edges on the PAI pin to increment the
counter.
In event counter mode (PAMOD = 0):
1 Rising PAI edge increments counter
0 Falling PAI edge increments counter
In gated time accumulation mode (PAMOD = 1):
1 Low PAI input enables divide-by-64 clock to pulse accumulator and trailing rising
0 High PAI input enables divide-by-64 clock to pulse accumulator and trailing falling
Note: The timer prescaler generates the divide-by-64 clock. If the timer is not active,
there is no divide-by-64 clock.
To operate in gated time accumulation mode:
1. Apply logic 0 to RSTI pin.
2. Initialize registers for pulse accumulator mode test.
3. Apply appropriate level to PAI pin.
4. Enable GPT.
Select the GPT counter input clock. Changing the CLK bits causes an immediate
change in the GPT counter clock input.
00 GPT prescaler clock (When PAE = 0, the GPT prescaler clock is always the GPT
01 PACLK
10 PACLK/256
11 PACLK/65536
Table 20-18. GPTPACTL Field Descriptions
edge on PAI sets PAIF flag.
edge on PAI sets PAIF flag.
counter clock.)
PAE
6
PAMOD PEDGE
IPSBAR + 0x1A_0018, 0x1B_0018
5
0000_0000
4
R/W
3
Description
CLK
PAOVI
Freescale Semiconductor
PAI
0