MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 523

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

26.3.2.12 Port QS Pin Assignment Register (PQSPAR)
The PQSPAR controls the pin function of port QS.
Freescale Semiconductor
Bits
5–0
7
6
Address
Address
Reset
Reset
Field
R/W:
Field
R/W:
Bits
7
6
PEHPA
PELPA
Name
—
PEHPA
—
R
7
7
Figure 26-25. Port EH/EL Pin Assignment Register (PEHLPAR)
Port EH pin assignment. This bit configures the port EH pins for its primary functions (ETXCLK,
ETXEN, ETXD[0], ECOL, ERXCLK, ERXDV, ERXD[0], ECRS) or digital I/O.
0 Port EH pins configured for digital I/O
1 Port EH pins configured for primary functions (ETXCLK, ETXEN, ETXD[0], ECOL, ERXCLK,
Note: This bit is reserved for the MCF5214 and MCF5216.
Port EL pin assignment. This bit configures the port EL pins for their primary functions (ETXD[3],
ETXD[2], ETXD[1], ETXER, ERXD[3], ERXD[2], ERXD[1], ERXER) or digital I/O.
0 Port EL pins configured for digital I/O
1 Port EL pins configured for primary functions (ETXD[3], ETXD[2], ETXD[1], ETXER, ERXD[3],
Note: Setting 1 is reserved for the MCF5214 and MCF5216.
Reserved, should be cleared.
R/W
Figure 26-26. Port QS Pin Assignment Register (PQSPAR)
ERXDV, ERXD[0], ECRS)
ERXD[2], ERXD[1], ERXER)
PQSPA6
PQSPA6
Name
PELPA
—
6
6
Table 26-15. PEHLPAR Field Descriptions
Table 26-16. PQSPAR Field Description
PQSPA5
Reserved, should be cleared.
Port QS pin assignment 6. This bit configures the port QS6 pin for its
primary function (QSPI_CS3) or digital I/O.
1 Port QS6 pin configured for primary function (QSPI_CS3)
0 Port QS6 pin configured for digital I/O
5
5
IPSBAR + 0x10_0058
IPSBAR + 0x10_0059
PQSPA4
4
0000_0000
0000_0000
Description
PQSPA3
R/W
3
Description
—
R
PQSPA2
2
PQSPA1
1
General Purpose I/O Module
PQSPA0
0
0
26-23