MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 428

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

UART Modules
23.3.3
The USRn registers show the status of the transmitter, the receiver, and the FIFO.
23-8
TXRDY
TEMP
Field
RB
OE
FE
PE
7
6
5
4
3
2
IPSBAR
Offset:
Reset:
Received break. The received break circuit detects breaks originating in the middle of a received character. However,
a break in the middle of a character must persist until the end of the next detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check
Parity error. Valid only if RXRDY is set.
0 No parity error occurred.
1 If UMR1n[PM] equals 0x (with parity or force parity), the corresponding character in the FIFO was received with
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character
Transmitter empty.
0 The transmit buffer is not empty. A character is shifted out, or the transmitter is disabled. The transmitter is
1 The transmitter has underrun (the transmitter holding register and transmitter shift registers are empty). This bit
Transmitter ready.
0 The CPU loaded the transmitter holding register, or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the
W
R
occupied when a break is received. Further entries to the FIFO are inhibited until URXDn returns to the high state
for at least one-half bit time, which equals two successive edges of the UART clock. RB is valid only when RXRDY
is set.
occurs in the middle of the first stop-bit position. FE is valid only when RXRDY is set.
incorrect parity. If UMR1n[PM] equals 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid
only when RXRDY is set.
when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this
occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any,
are lost. The
enabled/disabled by programming UCRn[TC].
is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding
register awaiting transmission.
transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded
into the transmitter holding register are not sent.
UART Status Registers (USRn)
0x00_0204 (USR0)
0x00_0244 (USR1)
0x00_0284 (USR2)
RB
0
7
RESET ERROR STATUS
FE
0
6
Figure 23-5. UART Status Registers (USRn)
Table 23-5. USRn Field Descriptions
PE
0
5
command in UCRn clears OE.
OE
0
4
Description
TXEMP
0
3
TXRDY
0
2
Access: User read-only
FFULL
Freescale Semiconductor
1
0
RXRDY
0
0